Hardware tweaking and software interfacing for neuromorphic chips

Experience the pain. Neuromorphic hardware chips provide a platform for the physical implementation and verification of variety of algorithms enabling the investigation of a number of computational approaches. Towards this end, several neuromorphic hardware chips were brought to the workshop.

INI Zurich chip

HiAER-IFAT system from University of California San Diego (UCSD)

The hierarchical address-event routing and integrate-and-fire (HiAER) system consists of 4 chips consisting of 65k neuron integrate-and-fire transceiver with address-event reconfigurable synaptic routing (as described in ISCAS 2012 and EMBC 2012).

This shows the output spikes from the HiAER-IFAT system.

Software interfacing with neuromorphic chips

In order to facilitate a user's interactions and testing of a single algorithm across a set of different hardware implementations, we discussed the development of a common software interface protocol. Describe PyNCS format.