2011/asyn11: alt.v

File alt.v, 7.5 KB (added by rajit, 7 years ago)
Line 
1//----------------------------------------
2//  act process: sink<>
3//  flavor: none
4//----------------------------------------
5module sink(gen__CLK, \g.Reset , \in.f , \in.t , \in.e );
6  input gen__CLK; wire gen__CLK;
7 input \g.Reset ;
8 wire \g.Reset ;
9 input \in.f ;
10 wire \in.f ;
11 input \in.t ;
12 wire \in.t ;
13 output \in.e ;
14 reg \in.e ;
15
16
17/* internal signals */
18always @(posedge gen__CLK) begin
19  if (((!(\g.Reset ) && !(\in.f )) && !(\in.t )))\in.e  <= 1'b1;
20 else   if (((\g.Reset  || \in.f ) || \in.t ))\in.e  <= 1'b0;
21end
22endmodule
23//----------------------------------------
24//  act process: wchb_tokenin<>
25//  flavor: none
26//----------------------------------------
27module wchb_tokenin(gen__CLK, \g.Reset , \l.f , \l.t , \l.e , \r.f , \r.t , \r.e );
28  input gen__CLK; wire gen__CLK;
29 input \g.Reset ;
30 wire \g.Reset ;
31 input \l.f ;
32 wire \l.f ;
33 input \l.t ;
34 wire \l.t ;
35 output \l.e ;
36 reg \l.e ;
37 output \r.f ;
38 reg \r.f ;
39 output \r.t ;
40 reg \r.t ;
41 input \r.e ;
42 wire \r.e ;
43
44
45/* internal signals */
46 reg \__d1 ;
47 reg \rv ;
48 reg \__d0 ;
49always @(posedge gen__CLK) begin
50  if (!(\__d1 )) \r.t  <= 1'b1;
51  else \r.t  <= 1'b0;
52end
53always @(posedge gen__CLK) begin
54  if ((\g.Reset  || (!(\r.e ) && !(\l.t ))))\__d1  <= 1'b1;
55 else   if (((!(\g.Reset ) && \r.e ) && \l.t ))\__d1  <= 1'b0;
56end
57always @(posedge gen__CLK) begin
58  if (!(\rv )) \l.e  <= 1'b1;
59  else \l.e  <= 1'b0;
60end
61always @(posedge gen__CLK) begin
62  if (!(\__d0 )) \r.f  <= 1'b1;
63  else \r.f  <= 1'b0;
64end
65always @(posedge gen__CLK) begin
66  if (!((\__d0  && \__d1 ))) \rv  <= 1'b1;
67  else \rv  <= 1'b0;
68end
69always @(posedge gen__CLK) begin
70  if ((\g.Reset  || (!(\r.e ) && !(\l.f ))))\__d0  <= 1'b1;
71 else   if (((!(\g.Reset ) && \r.e ) && \l.f ))\__d0  <= 1'b0;
72end
73endmodule
74//----------------------------------------
75//  act process: init_token<1>
76//  flavor: none
77//----------------------------------------
78module init_token_1_(gen__CLK, \g.Reset , \in.f , \in.t , \in.e , \out.f , \out.t , \out.e );
79  input gen__CLK; wire gen__CLK;
80 input \g.Reset ;
81 wire \g.Reset ;
82 input \in.f ;
83 wire \in.f ;
84 input \in.t ;
85 wire \in.t ;
86 output \in.e ;
87 reg \in.e ;
88 output \out.f ;
89 output \out.t ;
90 input \out.e ;
91 wire \out.e ;
92
93
94/* internal signals */
95 reg \__d[1] ;
96 reg \__d[0] ;
97 reg \rv ;
98 reg \x.t ;
99 wire \x.e ;
100 reg \x.f ;
101always @(posedge gen__CLK) begin
102  if ((!(\x.e ) && !(\in.t )))\__d[1]  <= 1'b1;
103 else   if ((\g.Reset  || (\x.e  && \in.t )))\__d[1]  <= 1'b0;
104end
105always @(posedge gen__CLK) begin
106  if ((\g.Reset  || (!(\x.e ) && !(\in.f ))))\__d[0]  <= 1'b1;
107 else   if ((\x.e  && \in.f ))\__d[0]  <= 1'b0;
108end
109always @(posedge gen__CLK) begin
110  if (!((\__d[0]  && \__d[1] ))) \rv  <= 1'b1;
111  else \rv  <= 1'b0;
112end
113always @(posedge gen__CLK) begin
114  if (!(\rv )) \in.e  <= 1'b1;
115  else \in.e  <= 1'b0;
116end
117always @(posedge gen__CLK) begin
118  if (!(\__d[1] )) \x.t  <= 1'b1;
119  else \x.t  <= 1'b0;
120end
121always @(posedge gen__CLK) begin
122  if (!(\__d[0] )) \x.f  <= 1'b1;
123  else \x.f  <= 1'b0;
124end
125 wchb_tokenin w (gen__CLK, \g.Reset , \x.f , \x.t , \x.e , \out.f , \out.t , \out.e  );
126endmodule
127//----------------------------------------
128//  act process: invert<>
129//  flavor: none
130//----------------------------------------
131module invert(gen__CLK, \g.Reset , \in.f , \in.t , \en , \out.f , \out.t , \out.e );
132  input gen__CLK; wire gen__CLK;
133 input \g.Reset ;
134 wire \g.Reset ;
135 input \in.f ;
136 wire \in.f ;
137 input \in.t ;
138 wire \in.t ;
139 output \en ;
140 reg \en ;
141 output \out.f ;
142 reg \out.f ;
143 output \out.t ;
144 reg \out.t ;
145 input \out.e ;
146 wire \out.e ;
147
148
149/* internal signals */
150 reg \__d[1] ;
151 reg \outv ;
152 reg \__inv ;
153 reg \__en ;
154 reg \__d[0] ;
155 reg \____en ;
156 reg \in__v ;
157always @(posedge gen__CLK) begin
158  if ((!(\en ) && !(\out.e )))\__d[1]  <= 1'b1;
159 else   if (((\en  && \out.e ) && \in.f ))\__d[1]  <= 1'b0;
160end
161always @(posedge gen__CLK) begin
162  if (!(\__d[1] )) \out.t  <= 1'b1;
163  else \out.t  <= 1'b0;
164end
165always @(posedge gen__CLK) begin
166  if (!(\__d[0] )) \out.f  <= 1'b1;
167  else \out.f  <= 1'b0;
168end
169always @(posedge gen__CLK) begin
170  if ((!(\__d[0] ) || !(\__d[1] )))\outv  <= 1'b1;
171 else   if ((\__d[0]  && \__d[1] ))\outv  <= 1'b0;
172end
173always @(posedge gen__CLK) begin
174  if (!((\in.f  || \in.t ))) \__inv  <= 1'b1;
175  else \__inv  <= 1'b0;
176end
177always @(posedge gen__CLK) begin
178  if (!(\____en )) \__en  <= 1'b1;
179  else \__en  <= 1'b0;
180end
181always @(posedge gen__CLK) begin
182  if ((!(\en ) && !(\out.e )))\__d[0]  <= 1'b1;
183 else   if (((\en  && \out.e ) && \in.t ))\__d[0]  <= 1'b0;
184end
185always @(posedge gen__CLK) begin
186  if (((!(\g.Reset ) && !(\outv )) && !(\in__v )))\____en  <= 1'b1;
187 else   if ((\g.Reset  || (\outv  && \in__v )))\____en  <= 1'b0;
188end
189always @(posedge gen__CLK) begin
190  if (!(\__en )) \en  <= 1'b1;
191  else \en  <= 1'b0;
192end
193always @(posedge gen__CLK) begin
194  if (!(\__inv )) \in__v  <= 1'b1;
195  else \in__v  <= 1'b0;
196end
197endmodule
198//----------------------------------------
199//  act process: wchb_buf<>
200//  flavor: none
201//----------------------------------------
202module wchb_buf(gen__CLK, \g.Reset , \in.f , \in.t , \in.e , \out.f , \out.t , \out.e );
203  input gen__CLK; wire gen__CLK;
204 input \g.Reset ;
205 wire \g.Reset ;
206 input \in.f ;
207 wire \in.f ;
208 input \in.t ;
209 wire \in.t ;
210 output \in.e ;
211 reg \in.e ;
212 output \out.f ;
213 reg \out.f ;
214 output \out.t ;
215 reg \out.t ;
216 input \out.e ;
217 wire \out.e ;
218
219
220/* internal signals */
221 reg \__d1 ;
222 reg \rv ;
223 reg \__d0 ;
224always @(posedge gen__CLK) begin
225  if (!(\__d1 )) \out.t  <= 1'b1;
226  else \out.t  <= 1'b0;
227end
228always @(posedge gen__CLK) begin
229  if (!(\__d0 )) \out.f  <= 1'b1;
230  else \out.f  <= 1'b0;
231end
232always @(posedge gen__CLK) begin
233  if ((!(\out.e ) && !(\in.t )))\__d1  <= 1'b1;
234 else   if ((\out.e  && \in.t ))\__d1  <= 1'b0;
235end
236always @(posedge gen__CLK) begin
237  if (!(((!(\g.Reset ) && \__d0 ) && \__d1 ))) \rv  <= 1'b1;
238  else \rv  <= 1'b0;
239end
240always @(posedge gen__CLK) begin
241  if (!(\rv )) \in.e  <= 1'b1;
242  else \in.e  <= 1'b0;
243end
244always @(posedge gen__CLK) begin
245  if ((!(\out.e ) && !(\in.f )))\__d0  <= 1'b1;
246 else   if ((\out.e  && \in.f ))\__d0  <= 1'b0;
247end
248endmodule
249//----------------------------------------
250//  act process: copy2<>
251//  flavor: none
252//----------------------------------------
253module copy2(gen__CLK, \g.Reset , \in.f , \in.t , \in.e , \out[0].f , \out[0].t , \out[0].e , \out[1].e );
254  input gen__CLK; wire gen__CLK;
255 input \g.Reset ;
256 wire \g.Reset ;
257 input \in.f ;
258 wire \in.f ;
259 input \in.t ;
260 wire \in.t ;
261 output \in.e ;
262 output \out[0].f ;
263 output \out[0].t ;
264 input \out[0].e ;
265 wire \out[0].e ;
266 input \out[1].e ;
267 wire \out[1].e ;
268
269
270/* internal signals */
271 reg \__en ;
272 reg \w.out.e ;
273always @(posedge gen__CLK) begin
274  if ((!(\out[0].e ) && !(\out[1].e )))\__en  <= 1'b1;
275 else   if ((\out[0].e  && \out[1].e ))\__en  <= 1'b0;
276end
277always @(posedge gen__CLK) begin
278  if (!(\__en )) \w.out.e  <= 1'b1;
279  else \w.out.e  <= 1'b0;
280end
281 wchb_buf w (gen__CLK, \g.Reset , \in.f , \in.t , \in.e , \out[0].f , \out[0].t , \w.out.e  );
282endmodule
283//----------------------------------------
284//  act process: toplevel<>
285//  flavor: none
286//----------------------------------------
287module toplevel(gen__CLK, \g.Reset , \out.f , \out.t , \out.e );
288  input gen__CLK; wire gen__CLK;
289 input \g.Reset ;
290 wire \g.Reset ;
291 output \out.f ;
292 output \out.t ;
293 output \out.e ;
294
295
296/* internal signals */
297 sink s (gen__CLK, \g.Reset , \out.f , \out.t , \out.e  );
298 init_token_1_ init (gen__CLK, \g.Reset , \out.f , \out.t , \c.out[0].e , \inv.in.f , \inv.in.t , \inv.en  );
299 invert inv (gen__CLK, \g.Reset , \inv.in.f , \inv.in.t , \inv.en , \c.in.f , \c.in.t , \c.in.e  );
300 copy2 c (gen__CLK, \g.Reset , \c.in.f , \c.in.t , \c.in.e , \out.f , \out.t , \c.out[0].e , \out.e  );
301endmodule